Method and system for fast memory access

ABSTRACT

An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Provisional U.S. Patent ApplicationNo. 60/301,458, filed Jun. 29, 2001, which is incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to methods and systems for fast access ofcomputer-based memories.

2. Related Art

Modern computer-based systems often use wide memories that have aconstant width. However, these systems must often manipulate a varietyof variables having different data widths. For instance, a particularprocessor can have a thirty-two bit (four byte) wide bus with athirty-two bit wide random access memory (RAM), but must manipulate anynumber of variables having eight bit (one byte), sixteen bit (two bytes)or thirty-two bit widths.

One problem that can arise with such systems is that data can becomemisaligned with the physical boundaries of the available memory. Forexample, a first variable in a block of thirty-two bit wide RAM may be abyte-wide variable while a second variable may be a four-byte variable.As a result, the first variable will occupy the first byte of a firstmemory location, while the second variable will occupy the remainingthree bytes of the first memory location plus the first byte of the nextmemory location. One unfortunate consequence of this situation is that acomputer accessing the second variable can take two separatememory-access cycles to either read or write the second variable.

While various approaches are available to align various variables havingdifferent bit-widths with the address boundaries of a memory, theseapproaches typically require a wasteful use of available memoryresources or otherwise cannot be used with practicable systems.Accordingly, new technologies that can eliminate multiple-cycle memoryaccesses for misaligned data are desirable.

SUMMARY OF THE INVENTION

The invention provides techniques to access a misaligned data word in asingle memory-access cycle. In various embodiments, the techniques use afirst memory section connected to a first address bus, a second memorysection connected to a second address bus and an address device thatsimultaneously provides a first address to the first memory sectionusing the first address bus and a second, incrementally higher, addressto the second memory section using the second address bus. The first andsecond memory sections are preferably separate memory arrays.

When the access operation is a read operation, buffer circuitry canreceive a first portion of the misaligned data word from the firstmemory section and receive a second portion of the misaligned data wordfrom the second memory section and assemble the data in the data wordfrom the first and second portions. When the access operation is a writeoperation, the buffer circuitry can effectively perform a shiftoperation on the data in the data word, then write a first portion ofthe shifted word to the first memory section and write a second portionof the shifted word to the second memory section.

Accordingly, data accesses that would take two memory-access cycles on aconventional memory system are reduced to a single memory-access cycle.Others features and advantages will become apparent in the followingdescriptions and accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in detail with regard to the followingfigures, wherein like numerals reference like elements, and wherein:

FIG. 1 is a block diagram of an exemplary system capable of accessingmisaligned data in a single memory-access cycle according to the presentinvention;

FIG. 2 is a block diagram of the memories of FIG. 1;

FIGS. 3A and 3B depicts a first memory access operation according to thepresent invention;

FIGS. 4A-4C depicts a second memory access operation according to thepresent invention;

FIG. 5 is a block diagram of a second exemplary system capable ofaccessing misaligned data in a single cycle according to the presentinvention;

FIG. 6 is a flowchart outlining a first exemplary operation according tothe present invention; and

FIG. 7 is a flowchart outlining a second exemplary operation accordingto the present invention.

DESCRIPTION OF RELATED ART

A frequent problem that arises with modern computer-based systems isthat, while the widths of an available physical memory are fixed, thewidths of various data types can vary. For example, a particularmicrocomputer may have a sixty-four bit wide memory, but may be requiredto access and manipulate eight-bit, sixteen-bit, thirty-two bit andsixty-four bit data. One problem that can arise with such systems isthat different data variables can become misaligned with the addressboundaries of the physical memories. For example, the first variable ina block of sixty-four bit wide memory may be a single byte-widevariable, while the second variable may be an eight byte-wide variable.As a result, the first variable will occupy a first byte of the firstmemory location, and the second variable will occupy the remaining sevenbytes of the first memory location plus the first byte of the nextmemory location. One unfortunate consequence of this situation is that aprocessor accessing the second variable can require two separatememory-access cycles to either read or write the second variable.

However, by providing two separate physical memories each beingsixty-four bits wide and further providing various circuitry that canmake the two memories appear as a single memory where the addressedmemory locations of the first memory are interleaved with those of thesecond memory location, misaligned data can be accessed in a singlememory-access cycle. For the example above, the eight-byte misaligneddata variable can be written in a single memory-access cycle bysplitting the eight-byte variable into a first portion having the firstseven bytes and a second portion having the last byte. Assuming thatseparate addresses and control signals are provided for each of the twophysical memories, the first portion of the data variable can then bewritten to the last seven bytes of the first memory while the secondportion can be simultaneously written to the first byte of the secondmemory. Similarly, data can be read by providing consecutive addressesto the first and second memories, selectively reading the desired bytesand then appropriately combining the selected bytes.

FIG. 1 is a block diagram of a system 100 capable of accessingmisaligned data in a single cycle according to the present invention. Asshown in FIG. 1, the system 100 includes a first data buffer block 110,and address device 130, a second data buffer block 140, an even memorysection 120-A and an odd memory section 120-B.

In a first operation, misaligned data can be written to the memorysections 120-A and 120-B in a single memory-access cycle. The exemplarymemory sections 120-A and 120-B are each sixty-four bit wide (eightbyte) devices each having 262,144 (2¹⁸) separate locations. However,rather than appear as single memory having a width of 128 bits by262,144 locations, the memory sections 120-A and 120-B can appear as asingle physical memory having a width of sixty-four bits and 524,288interleaved memory locations. For example, the first four memorylocations of memory section 120-A can appear as addressed locationszero, two, four, six and eight, while the first four memory locations ofmemory section 120-B can appear as addressed locations one, three, five,seven and nine.

During operation, an external device (not shown) writing to the memorysections 120-A and 120-B can provide a data word to the first databuffer block 110 via link 102, and further provide address and controlsignals to the address device 130 via links 104 and 106 respectively. Asthe address device 130 receives the address and control signals, theaddress device 130 can make a determination whether a particularvariable is misaligned, i.e., whether a particular data variable crossesthe sixty-four bit physical memory boundary.

If a particular data variable is misaligned, the address device 130 canprovide an offset to the first data buffer 110 via link 138-W. Forexample, if a particular eight-byte data variable is misaligned suchthat the first byte of the misaligned data variable is located at thesixth byte of the physical memory, the address device 130 can provide anoffset of five to the first data buffer block 110.

As the address device 130 provides the offset to the first data bufferblock 110, the address device 130 can further provide address andcontrol information to the memory sections 120-A and 120-B. Theappropriate addressing information is provided to the memory sections120-A and 120-B via links 132-A and 132-B, respectively. The writecontrol information is provided to the memory sections 120-A and 120-Bvia links 134-A and 134-B, respectively. For the example immediatelyabove, the address device 130 can provide a first address to memorysection 120-A and a second address to memory location 120-B, where thesecond address is incrementally larger than the first address.Simultaneously, the address device 130 can provide write controlinformation that can cause a write operation for the upper three bytesof the first memory section 120-A and the lower five bytes of the secondmemory section 120-B.

As the address device 130 provides address, control and offsetinformation, the first data buffer block 110 can receive the datavariable along with the offset information, manipulate and divide thedata into a first portion and second portion and appropriately feed thefirst portion to one memory section 120-A or 120-B and the secondportion to the other memory section 120-B or 120-A. A link 112-A conveysdata from the first data buffer 110 to the first memory section 120-Aand another link 112-B conveys data from the first buffer 110 to thesecond memory section 120-B. Again, for the example above, assuming thereceived data variable is eight bytes wide and has an offset of five,the first data buffer block 110 can direct the low three bytes of thedata variable to the high three bytes of memory section 120-A, andfurther provide the high five bytes of the data variable to the low fivebytes of memory section 120-B.

As the data variable is provided to the memory sections 120-A and 120-B,the memory sections 120-A and 120-B can receive their respective dataportions along with the address and control information andappropriately store the data. That is, memory section 120-A can storethe low three bytes of the data variable in the high three bytes of amemory location having a first address, while memory section 120-B canstore the high five bytes of the data variable in the low five bytes ofa memory location having a second address, where the second address willbe one location higher than the first address. Accordingly, as data isprovided to the various memory sections 120-A and 120-B, the address andcontrol information can simultaneously accommodate a misaligned writeoperation to both memory locations in a single cycle.

In a second operation, the system 100 can read a misaligned datavariable from the memory sections 120-A and 120-B. During operation, asan external device provides the appropriate address and control signalsvia links 104 and 106 respectively, the address device 130 can receivethe address and control signals, provide an offset to the second databuffer block 140 via link 138-R, provide the appropriate addressinginformation to memory sections 120-A and 120-B via links 132-A and 132-Brespectively and further provide the appropriate read controlinformation to memory sections 120-A and 120-B via links 136-A and 136-Brespectively.

The memory sections 120-A and 120-B can receive the address and readcontrol information and provide the appropriate bytes of data to thesecond data buffer 140 via links 122-A and 122-B. The second data bufferblock 140 in turn can receive the data bytes from the memory sections120-A and 120-B and combine the received data bytes into a single datavariable taking into account the offset provided by the address device130. For example, assuming that an eight-byte data variable is read withthe low two bytes provided by the high two bytes of memory section 120-Aand the remaining six bytes provided by the low six bytes of memorysection 120-B (which assumes a data offset of six), the second databuffer block 140 can receive the various bytes, combine the variousbytes into a single contiguous data variable having eight bytes,appropriately shift the combined data variable by six bytes and providethe combined/shifted data variable to an external device.

The exemplary first data buffer block 110 can be a portion of integratedcircuit containing various logic circuits that can receive a datavariable of a given size, effectively perform a circular-barrelshift/multiplexing operation on the received data variable and provideportions of the shifted/multiplexed data variable to the memory sections120-A and 120-B. However, it should be appreciated that, in variousembodiments, the first data buffer block can use any combination ofelements, such as shifters, barrel shifters, multiplexers, varioussum-of-products-based logic, or any other known or later developedcombination of systems and devices that can receive a data variable,perform the equivalent of a shifting operation on the received datavariable and provide the shifted data to the memory sections 120-A and120-B without departing from the spirit and scope of the presentinvention.

The second data buffer block 140, like the first data buffer 110, can bea portion of an integrated circuit containing various logic circuits.However, like the first data buffer block 110, it should be appreciatedthat the second data buffer block 140 can be any device capable ofreceiving various portions of data from multiple memories, combine thereceived data portions, and provide the combined data to an externaldevice without departing from the spirit and scope of the presentinvention.

The address device 130, like the first and second data buffer blocks 110and 140, can be a collection of logic circuits on a portion of anintegrated circuit. However, it should be appreciated that the addressdevice 130 can be any combination of systems and devices capable ofreceiving address and control signals from an external device andproviding address and control information to memory sections 120-A and120-B as well as offset information to the data buffers 110 and 130without departing from the spirit and scope of the present invention.

FIG. 2 depicts a memory system, such as the memory sections 120-A and120-B of FIG. 1. As shown in FIG. 2, the memory system 120 includes anumber of byte-wide memory modules 120-1, 120-2 . . . 120-k. The variousmemory modules 120-1, 120-2, . . . 120-k each have a data input port112-1, 112-2, . . . 112-k, a data output port 122-1, 122-2, . . . 122-k,an address port 132-1, 132-2, . . . 132-k, a write port 134-1, 134-2, .. . 134-k and a read port 136-1, 136-2, . . . 136-k.

In a first operation, a data can be selectively written to anycombination of the memory modules 120-1, 120-2, . . . 120-k by providingthe appropriate data to each of the data input ports 112-1, 112-2, . . .112-k via bus 112 while applying the appropriate address information tothe address ports 132-1, 132-2, . . . 132-k via bus 132 and writecontrol information, such as write strobes, to the appropriate writeports 134-1, 134-2, . . . 134-k via bus 134.

Similarly, data can be read from the memory system 120, by providing theappropriate address information to the various address ports 132-1,132-2, . . . 132-k via bus 132 as well as the appropriate read controlinformation, such as read strobes, to the various read ports 136-1,136-2, . . . 136-k via bus 136. As the address and read controlinformation are received by the various memory modules 120-1, 120-2, . .. 120-k, it should be appreciated that the appropriate memory modules120-1, 120-2, . . . 120-k will enable output buffers associated withtheir output ports 122-1, 122-2, . . . 122-k such that data storedwithin each module 120-1, 120-2, . . . 120-k can be provided to data-bus122. It should also be appreciated that because read operations do notgenerally alter the contents of a memory module, the array of individualread strobes can be replace by a single read strobe with theunderstanding that using a single read strobe may cause the memorysystem 120 to use more power.

While the exemplary memory modules 120-1, 120-2, . . . 120-k arecontrolled using read and write strobes, it should be appreciated thatin various embodiments, the various memory modules 120-1, 120-2, . . .120-k can be controlled using a variety of signals including readstrobes, write strobes, chip selects, output enable signals, or anyother signal useful for selectively writing data to, or reading datafrom, a memory device without departing from the spirit and scope of thepresent invention.

The exemplary memory modules 120-1, 120-2, . . . 120-k are high-speedrandom access memory (RAM) integrated circuits with each device beingeight bits wide and having 242,144 separate locations. However, itshould be appreciated that the various memory modules 120-1, 120-2, . .. 120-k can be any other known memory device capable of beingselectively read or written to, such as RAMs, read only memories (ROMs),EPROMs, EEPROMs, and the like. It should further be appreciated that theparticular width and depth of each memory module, 120-1, 120-2, . . .120-k can vary as desired or otherwise required by design, withoutdeparting from the spirit and scope of the present invention.

FIGS. 3A and 3B depict the operations of a misaligned data word beingwritten to a system, such as a memory system depicted in FIGS. 1 and 2.As shown in FIG. 3A, a data variable {d7 . . . d0} can be misalignedwith respect to a physical memory consisting of eight bytes {b7 . . .b0}. Although the logical width of a physical memory may appear as eightbytes {b7 . . . b0}, as discussed above the actual physical data widthcan be sixteen bytes {b7 . . . b0, b7 . . . b0} of data including anumber of odd memory bytes 312 and even memory bytes 314.

Because the exemplary data variable is offset by two bytes, the low sixbytes of the data variable {d5 . . . d0} can be written to the highbytes {b7 . . . b2} respectively of the even memory bytes 314.Similarly, high two data variable bytes {d7, d6} can be written to thetwo low memory bytes {b1, b0} respectively of the odd memory bytes 312.

FIG. 3B depicts the data variable {d7 . . . d0} shown in FIG. 3A brokeninto an even portion 322 consisting of data variable bytes {d5 . . . d0}and an odd portion 334 consisting of data variable bytes {d7, d6}. Asshown in FIG. 3B, because only the high six bytes of the even portion322 are to be written to, write enable signals=“11111100” representingan array of write strobes can be provided to an array of individualbyte-wide memory modules of an even memory (at a relative address of“00000”) to activate write operations at the appropriate memory modules.Similarly, because only the low two bytes of the odd portion 324 are tobe written, a write enable signals of “00000011” can be similarlyapplied to another array of memory modules at a relative address of“01000” to activate write operations at the appropriate odd memorymodules.

FIGS. 4A-4C depict a second memory access operation where a four-bytedata variable {d3 . . . d0} can be read from a memory system capable ofreading a misaligned data variable in a single cycle. As shown in FIG.4A, the data variable {d3 . . . d0} has an offset of five bytes suchthat data variable bytes {d2, d1, d0} can be read from the high threememory bytes {b7, b6, b5} of even memory bytes 414 and data variablebyte {d3} can be read from the low memory byte {b0} of odd memory bytes412.

FIG. 4B depicts the data variable {d3 . . . d0} of FIG. 4A broken intoan even portion 422 and an odd portion 424 with data variable bytes {d2,d1, d0} included in the even portion 422 and data variable byte {d3}included in the odd portion 424. Since only the upper three bytes {b7,b6, b5} of the even portion 422 are to be read, read enable signals of“11100000” can be applied to respective byte-wide memory modules of aneven portion memory. Similarly, because only data byte {b0} is to beread from the odd portion 424, read enable signals of “00000001” can beapplied to an array of memory modules that comprise an odd memory. FIG.4C demonstrates that the bytes of the data variable {d3 . . . d0} can becombined and shifted such that the various bytes {d3 . . . d0} of thedata variable are respectively aligned with memory bytes {b3 . . . b0}.

FIG. 5 is a second exemplary embodiment of a system 500 capable ofreading and writing misaligned data variables in a single memory-accesscycle. As shown in FIG. 5, the system 500 includes a controller 502, aneven memory section 520-A and an odd memory section 520-B. Thecontroller 502 includes a data buffer block 510 and an address device530. As with the memory system 100 of FIG. 1, the second memory system500 can read and write misaligned data bytes. However, unlike the memorysystem 100 of FIG. 1, the second memory system 500 can read and writedata using a bi-directional bussed system.

In a write operation, the data buffer block 510 can generate orotherwise derive data from controller 502, optionally shift the data,and provide the data to the even and odd memory sections 520-A and520-B. Simultaneously, the address device 530 can provide even addressinformation and even write control information to the even memorysection 520-A via links 114-A and 118-A respectively, and furtherprovide odd address information and odd write control information to theodd memory section 520-B via links 114-B and 118-B respectively.

As discussed above, if a particular data variable is misaligned, theaddress device 530 can provide different address information to thedifferent memory sections 520-A and 520-B, as well as a different writecontrol information, such as an array of write strobes. Accordingly, byusing the above-described technique, a data variable can be written tothe memory sections 520-A and 520-B in a single memory-access cycleregardless of how the data variable is aligned.

In a second operation, the controller 502 can read a data variable fromthe memory sections 520-A and 520-B in a single cycle regardless of thealignment of the data variable. During operation, the address device 530can provide the appropriate addresses information as well as theappropriate read control information, such as an array of read strobes,to each of the even and odd memory sections 520-A and 520-B. As thememory sections 520-A and 520-B provide the requisite data bytes to thedata buffer 510, the data buffer block 510 can receive the appropriatedata bytes, then combine and shift the data bytes as is required by aparticular operation of the controller 502.

While the address device 530 is depicted as generating two differentaddresses using two disjoint address busses 114-A and 114-B, it shouldbe appreciated that in various embodiments, the address device 530 canprovide address information using address busses that are partiallydisjoint. For example, assuming the address device 530 is a sixteen-bitaddress device, the address device 530 can provide the most significanteight address bits to both the even and odd memory sections 520-A and520-B using eight shared address lines {A15 . . . A8}, while providingtwo separate sets of least significant address bits {A7 . . . A0}_(even)and {A7 . . . A0}_(odd) to memory sections 520-A and 520-B respectively.

While providing partially disjoint address busses does not allow thesystem 500 to access every possible misaligned memory location in asingle memory-access cycle, the total number of address lines isotherwise reduced. For the example above, assuming the address bus issixteen bits wide with the upper most eight bits being shared, a singlememory-access cycle access can be performed for 255 out of every 256memory locations. However, the controller 502 requires eight feweraddress ports/pins and supporting electronic circuits.

The exemplary controller 502 can be a microcontroller-type device on anintegrated circuit. However, it should be appreciated that thecontroller 502 can be any of various sequential instruction machines,such as a controller, a microcontroller, microprocessor, a processor, adigital signal processor or any other known or later developed devicethat can act as a sequential instruction machine and access variousmemories.

FIG. 6 is a block diagram of a flowchart of a first exemplary operationaccording to the present invention. The process starts at step 600 wherea data variable type is determined, i.e., the size of the data variable,as well as the address that the data variable is to be read from. Next,in step 610, a determination is made as to whether the data variable isaligned. That is, it is determined whether the data of the data variableexists in two separate logical memory locations. If the data variable isaligned, control jumps to steps 680; otherwise, control continues tostep 620. In step 680, data is read from a memory and control continuesto step 650.

In step 620, even and odd address information, as well as even and oddread control information, is provided to each of two memory sections,such as the even and odd memory sections shown in FIGS. 1 and 5. Next,in step 630, even and odd portions of the data variable are read fromthe even and odd memory sections. Then, in step 640, the even and oddportions are assembled into a single data variable. As discussed above,assembling a data variable can include logically combining the even andodd portions as well as shifting the combined portions such that theshifted data portions can be provided to an external device as a singledata variable aligned with the least significant bytes of a logical bus.Control continues to step 650.

In step 650, the assembled data of 640 is provided to another device,such as an integrated sequential instruction machine. Next, in step 660,a determination is made as to whether to continue reading datavariables. If further data variables are to be read, control jumps backto step 600; otherwise, control continues to step 670 where the processstops.

FIG. 7 is a flowchart outlining a second exemplary operation accordingto the present invention. As shown in FIG. 7, the process starts at step700 where the type and address of a particular data variable isdetermined. Next, at step 710, a determination is made as to whether thedata variable is aligned. If the data variable is aligned, control jumpsto step 800; otherwise, control continues to step 720. In step 800, datais written to a memory and control continues to step 760.

In step 720, even and odd address information, as well as even and oddwrite control information, is provided to even and odd memory sections.Next, in step 730, the data in the data variable is appropriatelyadjusted/manipulated by any of several operations that effectivelyperform a shifting operation such that the data can be provided to theappropriate memory modules of both an even and odd memory section. Then,in step 740, the data of the data variable is divided into an evenportion and an odd portion with the even portion provided to an evenmemory section and the odd portion provided to an odd memory section.Control continues to step 750.

In step 750, the even and odd portions are effectively written to theeven and odd memory sections. Next, in step 760, a determination is madeas to whether the data written in steps 700-750 is to be read. If datais to be read, control jumps to step 810; otherwise, control continuesto step 770.

In step 810, the appropriate data is read. In various embodiments, thedata read can be performed according to any number of techniques, suchas the technique outlined in the flowchart of FIG. 6 or describedaccording to FIGS. 1-5. Control continues to step 770.

In step 770, a determination is made as to whether to continue to writeand optionally read various data variables. If the operation is tocontinue, control jumps back to step 700; otherwise, control continuesto step 780 where the process stops.

As shown in FIG. 1-5, the systems and methods of this invention arepreferably implemented using dedicated logic or other integratedcircuits. However, the systems and methods can also be implemented usingany combination of one or more general purpose computers, specialpurpose computers, program microprocessors or microcontroller andperipheral integrating circuit elements, hardware electronic or logiccircuits such as application specific integrated circuits (ASICs),discrete element circuits, programmable logic devices such as PLAs,FPGAs, PALs or the like. In general, any device on which exists a finitestate machine capable of implementing the various elements of FIGS. 1-5and the flowcharts of FIGS. 6 and 7 can be used to implement thesequence of functions.

While this invention has been described in conjunction with the specificembodiments thereof, it is evident that many alternatives,modifications, and variations will be apparent to those skilled in theart. Accordingly, preferred embodiments of the invention as set forthherein are intended to be illustrative, not limiting. There are changesthat may be made without departing from the spirit and scope of theinvention.

1-37. (canceled)
 38. A method of accessing a misaligned data word,comprising: simultaneously providing a first address to a first memorysection using a first address bus and a second address that is not equalto the first address to a second memory section using a second addressbus; and accessing the misaligned data word by performing at least oneof a simultaneous read operation from the first and second memorysections and a simultaneous write operation to the first and secondmemory sections; wherein accessing the misaligned data word includesreading a first portion of the misaligned data word from the firstmemory section, and reading a second portion of the misaligned data wordfrom the second memory section.
 39. The method of claim 38, furthercomprising: assembling a word using the first and second word portions.40. A method of accessing a misaligned data word, comprising:simultaneously providing a first address to a first memory section usinga first address bus and a second address that is not equal to the firstaddress to a second memory section using a second address bus; andaccessing the misaligned data word by performing at least one of asimultaneous read operation from the first and second memory sectionsand a simultaneous write operation to the first and second memorysections; wherein accessing the misaligned data word includes writing afirst portion of the misaligned data word to the first memory section,and writing a second portion of the misaligned data word to the secondmemory section.
 41. The method of claim 40, wherein writing the firstportion and writing the second portion are performed in response toperforming a shift operation on the misaligned data word.
 42. The methodof claim 40, further comprising: providing write control informationsignals to a plurality of first modules of the first memory section,whereby write operations are activated on only those first modulesdesignated for data word information.
 43. A method of accessing amisaligned data word, comprising: simultaneously providing a firstaddress to a first memory section including a first number of bits usinga first address bus and a second address that is not equal to the firstaddress to a second memory section including a second number of bitsthat is same as the first number of bits using a second address bus; andaccessing the misaligned data word by performing at least one of asimultaneous read operation from the first and second memory sectionsand a simultaneous write operation to the first and second memorysections; wherein accessing the misaligned data word is performed in asingle cycle.
 44. A method of accessing a misaligned data word,comprising: simultaneously providing a first address to a first memorysection using a first address bus and a second address that is oneaddress location greater than the first address to a second memorysection using a second address bus; and accessing the misaligned dataword by performing at least one of a simultaneous read operation fromthe first and second memory sections and a simultaneous write operationto the first and second memory sections; wherein accessing themisaligned data word is performed in a single cycle.
 45. The method ofclaim 44, wherein simultaneously providing the first address and thesecond address is performed using the first and second address busseshaving at least one disjoint address line.
 46. The method of claim 44,wherein simultaneously providing the first address and the secondaddress is performed using the first and second address busses having atleast a plurality of disjoint address lines.
 47. The method of claim 46,wherein simultaneously providing the first address and the secondaddress is performed using the first and second address busses havingcompletely disjoint address lines.
 48. A method of accessing amisaligned data word, comprising: simultaneously providing a firstaddress to a first memory section using a first address bus and a secondaddress that is not equal to the first address to a second memorysection using a second address bus; accessing the misaligned data wordby performing at least one of a simultaneous read operation from thefirst and second memory sections and a simultaneous write operation tothe first and second memory sections; and providing a plurality of readcontrol information signals to a plurality of first modules of the firstmemory section, whereby read operations are activated on only thosefirst modules containing word data; wherein accessing the misaligneddata word is performed in a single cycle.
 49. The method of claim 48,further comprising: providing a plurality of write control informationsignals to the plurality of first modules of the first memory section,whereby write operations are activated on only those first modulesdesignated for data word information.
 50. A method of accessing amisaligned data word stored in first and second separately addressablememory arrays, comprising: storing a first portion of the misaligneddata word at a first location of a first memory array that includes evenaddress locations; storing a second portion of the misaligned data wordat a second location of a second memory array that includes odd addresslocations; simultaneously providing a first address indicating the firstlocation to the first memory array and a second address indicating thesecond location to the second memory array; and accessing the misaligneddata word by performing at least one of a simultaneous read operationfrom the first and second memory arrays and a simultaneous writeoperation to the first and second memory arrays; wherein accessing themisaligned data word is performed in a single cycle.